As bandwidth requirements for data transmission systems increase, there is a growing interest in transmitting parallel data at rates previously restricted to serial interfaces. As a consequence, the clock recovery techniques usually used for serial data transmission systems are now becoming relevant to parallel interfaces. In order to ensure the minimum error rate in the received data, each data channel of a parallel interface is provided with its own clock recovery circuit to capture the data. This approach negates the effects of variation in the transmission paths between channels that causes skew between the signals. However, this then produces a set of clocks, one for each channel, each of slightly different phase. These timing differences consequently hinder the use of a single common clock to operate all the receive (RX) channels in synchronism.
Having captured the high-speed serial data signals, it is common practice to demultiplex these into a parallel bus operating at a lower rate in order to alleviate the speed requirements of the subsequent circuitry. If the RX channels for the individual bits are operating independently on separate recovered clocks, this presents further difficulties in obtaining synchronized operation of the demultiplexing circuits. Without synchronization between the channels, it is difficult to sort the data bits from the demultiplexed outputs into the parallel data words originally transmitted.